The present disclosure relates to a semiconductor memory device, and more particularly to a deep power down mode control circuit.
Generally, when a semiconductor device is in an active state, peripheral circuits thereof operate to store data or to externally output stored data. On the other hand, in a standby state of the semiconductor device, unnecessary ones of the peripheral circuits are disabled to minimize power consumption.
In particular, mobile semiconductor memory devices use a deep power down mode for further reduction of power consumption in a standby state. The deep power down mode is adapted to further reduce current consumption, as compared to a power down mode. In the deep power down mode, an operation for internally switching off supply of power is basically carried out in spite of an application of a DRAM voltage.
That is, when a semiconductor memory device is in a standby mode for a prolonged period of time, it enters a deep power down mode, to stop operations of peripheral circuits, and thus, to reduce unnecessary power consumption occurring in the standby mode.
The deep power down mode is controlled in the semiconductor memory device in accordance with an external command.
That is, the semiconductor memory device enters or exits the deep power down mode in synchronism with a clock signal in accordance with the states of signals input to the semiconductor memory device via external signal pins, for example, a burst command and a clock enable signal.
For example, when the burst command signal is a stop signal, and the clock enable signal has a low level, the semiconductor memory device enters the deep power down mode in synchronism with a clock signal. When the clock enable signal transits to a high level, the semiconductor memory device exits the deep power down mode.
When the semiconductor memory device enters the deep power down mode, it is controlled in such a manner that supply of power to certain circuits of a power supply circuit is cut off, in order to reduce current consumption.
Referring to FIG. 1, a conventional deep power down control circuit is illustrated. The conventional deep power down control circuit includes a deep power down (DPD) signal generator 100, an internal voltage generator 200, an internal peripheral circuit controller 300, and a power up signal generator 400.
In such a conventional deep power down control circuit, however, the time when the semiconductor memory device enters the deep power down mode is not set. In the conventional case, only the time for internal voltage stabilization and circuit initialization, for example, 200 μm, is given, as shown in FIG. 2.
For this reason, there may be a problem in terms of an initialization of internal circuits when the period of time from the point of time when the semiconductor memory device enters the deep power down mode to the point of time when the semiconductor memory device exits the deep power down mode is very short.